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? semiconductor ML63187/63189b 1/35 general description the ML63187/63189b is a cmos 4-bit microcontroller with built-in 1024-dot matrix lcd drivers and operates at 0.9 v (min.). the ML63187/63189b is suitable for applications such as games, toys, watches, etc. which are provided with an lcd display. the ML63187/63189b is an m6318x series mask rom-version product of olms-63k family, which employs oki's original cpu core nx-4/250. features ? rich instruction set 408 instructions transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, rom table reference, stack operations, flag operations, branch, conditional branch, call/return, control. ? rich selection of addressing modes indirect addressing of four data memory types, with current bank register, extra bank register, hl register and xy register. data memory bank internal direct addressing mode. ? processing speed two clocks per machine cycle, with most instructions executed in one machine cycle. minimum instruction execution time : 61 m s (@ 32.768 khz system clock) 1 m s (@ 2 mhz system clock) ? clock generation circuit low-speed clock : crystal oscillation or rc oscillation selected with mask option (30 to 80 khz) high-speed clock : ceramic oscillation or rc oscillation selected with software (2 mhz max.) ? program memory space ? ML63187 : 16k words ? ml63189b : 32k words basic instruction length is 16 bits/1 word ? data memory space ? ML63187 : 1024 nibbles ? ml63189b : 1536 nibbles ? semiconductor ML63187/63189b 4-bit microcontroller with built-in 1024-dot matrix lcd drivers and melody circuit, operating at 0.9 v (min.) e2e0053-59-71 this version: jul. 1999 previous version: mar. 1999
? semiconductor ML63187/63189b 2/35 ? stack level call stack level : 16 levels register stack level : 16 levels ? i/o ports input ports: selectable as input with pull-up resistor/input with pull-down resistor/high- impedance input input-output ports: selectable as input with pull-up resistor/input with pull-down resistor/ high-impedance input selectable as p-channel open drain output/n-channel open drain output/cmos output/high-impedance output can be interfaced with external peripherals that use a different power supply than this device uses. number of ports: ML63187 input-output port : 2 ports 4 bits ml63189b input port : 1 port 4 bits input-output port : 4 ports 4 bits ? melody output melody frequency : 529 to 2979 hz tone length : 63 types tempo : 15 types melody data : resides in the program memory buzzer driver signal output : 4 khz ? lcd driver number of segments : 1024 max. (64 seg 16 com) 1/1 to 1/16 duty 1/4 or 1/5 bias (regulator built-in) selectable as all-on mode/all-off mode/power down mode/normal display mode adjustable contrast ? reset function reset through reset pin power-on reset reset by low-speed oscillation halt ? battery check low-voltage supply check the value of the judgment voltage is selected by the software by setting the ld1 and ld0 bits of bldcon. ld1 0 0 1 1 ld0 0 1 0 1 judgment voltage (v) 1.05 0.10 1.20 0.10 1.80 0.10 2.40 0.10 remarks ta = 25c ta = 25c ta = 25c ta = 25c
? semiconductor ML63187/63189b 3/35 ? power supply backup backup circuit (voltage multiplier) enables operation at 0.9 v minimum ? timers and counter 8-bit timer 4 selectable as auto-reload mode/capture mode/clock frequency measurement mode watchdog timer 1 100 hz timer 1 measurable in steps of 1/100 sec. 15-bit time base counter 1 1, 2, 4, 8, 16, 32, 64, and 128 hz signals can be read ? shift register shift clock : 1 or 1/2 system clock, timer 1 overflow, external clock data length : 8 bits ? interrupt sources ML63187 external interrupt : 2 internal interrupt : 12 (watchdog timer interrupt is a nonmask- able interrupt) ml63189b external interrupt : 3 internal interrupt : 12 (watchdog timer interrupt is a nonmask- able interrupt) ? operating temperature C20 to +70 c ? operating voltage when backup used : 0.9 to 2.7 v (operating frequency: 30 to 80 khz) 1.2 to 2.7 v (operating frequency: 300 to 500 khz) 1.5 to 2.7 v (operating frequency: 200 khz to 1 mhz) when backup not used : 1.8 to 5.5 v (operating frequency: 200 khz to 2 mhz) ? package: 128-pin plastic qfp (qfp128-p-1420-0.50-k) : (product name: ML63187-xxxga, ml63189b-xxxga) chip : ML63187-xxx, ml63189b-xxx xxx indicates a code number.
? semiconductor ML63187/63189b 4/35 block diagram (ML63187) an asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from v ddi (power supply for interface). rom 16kw bus con- trol mie xt0 xt1 osc0 osc1 osc cbr ebr l c g z alu ra a ir instruction decoder ram 1024n nx-4/250 reset rst v ddi pc h y x timing con- trol sp rsp stack cal : 16-level reg : 16-level timer 8bit 4 sclk* sin* sout* 4 int sft tm0cap/tm1cap* tm0ovf/tm1ovf* t02ck* t13ck* 1 int i/o port pb.0-pb.3 pe.0-pe.3 2 int v ddh v dd cb1 cb2 data bus tbc 4 int bld int 100hztc 1 back up v ss melody md 1 int mdb lcd & dspr com1-16 seg0-63 tst1 tst tst2 int wdt 1 v dd1 v dd2 v dd3 v dd4 v dd5 c1 c2 v ddl bias int187
? semiconductor ML63187/63189b 5/35 block diagram (ml63189b) an asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from v ddi (power supply for interface). rom 32kw bus con- trol mie xt0 xt1 osc0 osc1 osc cbr ebr l c g z alu ra a ir instruction decoder ram 1536n nx-4/250 reset rst v ddi pc h y x timing con- trol sp rsp stack cal : 16-level reg : 16-level timer 8bit 4 sclk* sin* sout* 4 int sft tm0cap/tm1cap* tm0ovf/tm1ovf* t02ck* t13ck* 1 int i/o port p9.0-p9.3 pa.0-pa.3 pb.0-pb.3 pe.0-pe.3 2 int v ddh v dd cb1 cb2 data bus tbc 4 int bld int 100hztc 1 back up v ss melody md 1 int mdb 1 int input port p0.0-p0.3 lcd & dspr com1-16 seg0-63 tst1 tst tst2 int wdt 1 v dd1 v dd2 v dd3 v dd4 v dd5 c1 c2 v ddl bias int189
? semiconductor ML63187/63189b 6/35 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (nc) (nc) (nc) (nc) seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 reset osc0 osc1 v ddl v dd cb2 cb1 v ddh c2 c1 v dd5 v dd4 v dd3 v dd2 v dd1 v ss com16 com15 com14 com13 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 (nc) (nc) (nc) (nc) seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com8 com7 com6 com5 com4 com3 com2 com1 pb.3 pb.2 pb.1 pb.0 pe.3 pe.2 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 31 32 33 34 35 36 37 38 com9 com10 com11 com12 (nc) (nc) (nc) (nc) 72 71 70 69 68 67 66 65 pe.1 pe.0 v ddi (nc) (nc) (nc) (nc) (nc) 64 63 62 61 60 59 mdb md tst2 tst1 xt0 xt1 seg12 seg13 seg14 seg15 seg16 seg17 103 104 105 106 107 108 pin configuration (top view) (ML63187) 128-pin plastic qfp note: pins marked as (nc) are no-connection pins which are left open.
? semiconductor ML63187/63189b 7/35 pad configuration (ML63187) pad layout chip size : 4.238 mm 4.914 mm chip thickness : 350 m m (280 m m: available as required) coordinate origin : center of chip pad hole size : 100 m m 100 m m pad size : 110 m m 110 m m minimum pad pitch : 140 m m note: the chip substrate voltage is v ss . y x 27 seg38 28 seg39 seg11 111 29 seg40 seg10 110 30 seg41 seg9 109 31 seg42 seg8 108 32 seg43 seg7 107 33 seg44 seg6 106 34 seg45 seg5 105 35 seg46 seg4 104 36 seg47 seg3 103 37 seg48 seg2 102 38 seg49 seg1 101 39 seg50 seg0 100 40 seg51 com8 99 41 seg52 com7 98 42 seg53 com6 97 43 seg54 com5 96 44 seg55 com4 95 45 seg56 com3 94 46 seg57 com2 93 47 seg58 com1 92 48 seg59 pb.3 91 49 seg60 pb.2 90 50 seg61 pb.1 89 seg30 19 seg29 18 57 com13 seg28 17 58 com14 seg27 16 59 com15 seg26 15 60 com16 seg25 14 61 v ss seg24 13 62 v dd1 seg23 12 63 v dd2 seg22 11 64 v dd3 seg21 10 65 v dd4 seg20 9 66 v dd5 seg19 8 67 c1 seg18 7 68 c2 seg17 6 69 v ddh seg16 5 70 cb1 seg15 4 71 cb2 seg14 3 72 v dd seg13 2 73 v ddl seg12 1 74 osc1 75 osc0 76 reset 77 xt1 78 xt0 79 tst1 80 tst2 81 md 82 mdb seg37 26 seg36 25 seg35 24 seg34 23 seg33 22 seg32 21 seg31 20 51 seg62 pb.0 88 52 seg63 pe.3 87 53 com9 pe.2 86 54 com10 pe.1 85 55 com11 pe.0 84 56 com12 v ddi 83 ML63187
? semiconductor ML63187/63189b 8/35 pad coordinates (ML63187) pad no. pad name x (m) y (m) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 pad no. pad name x (m) y (m) 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 pad no. pad name x (m) y (m) 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 37 38 39 40 41 73 74 75 76 77 108 78 79 80 81 82 109 110 111 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 com9 com10 com11 com12 com13 com14 com15 com16 v ss v dd1 v dd2 v dd3 v dd4 v dd5 c1 c2 v ddh cb1 cb2 v dd v ddl osc1 osc0 reset xt1 xt0 tst1 tst2 md mdb C1755 C1615 C1474 C1334 C1193 C1053 C913 C772 C632 C491 C351 C211 C70 70 211 351 491 632 772 913 1053 1193 1334 1474 1615 1755 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2311 C2036 C1895 C1755 C1615 C1474 C1334 C1193 C1053 C913 C772 C632 C491 C351 C211 1969 C70 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1755 1615 1474 1334 1193 1053 913 772 632 491 351 211 70 C70 C211 C351 C491 C632 C772 C913 C1053 C1193 C1334 C1474 70 211 351 491 632 772 913 1053 1193 1334 1474 1615 1755 1895 2036 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 C1615 C1755 2311 2311 v ddi pe.0 pe.1 pe.2 pe.3 pb.0 pb.1 pb.2 pb.3 com1 com2 com3 com4 com5 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 1895 1755 1615 1474 1334 1193 1053 913 772 632 491 351 211 70 com6 com7 com8 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C1969 C70 C211 C351 C491 C632 C772 C913 C1053 C1193 C1334 C1474 C1615 C1755 C1895 C2036
? semiconductor ML63187/63189b 9/35 58 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (nc) seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 osc1 v ddl v dd cb2 cb1 v ddh c2 c1 v dd5 v dd4 v dd3 v dd2 v dd1 v ss com16 com15 com14 com13 com12 com11 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 (nc) seg3 seg2 seg1 seg0 com8 com7 com6 com5 com4 com3 com2 com1 p0.3 p0.2 p0.1 p0.0 p9.3 p9.2 p9.1 p9.0 pa.3 pa.2 pa.1 pa.0 pb.3 pb.2 pb.1 pb.0 pe.3 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 31 32 33 34 35 36 37 38 seg59 seg60 seg61 seg62 seg63 com9 com10 (nc) 72 71 70 69 68 67 66 65 pe.2 pe.1 pe.0 v ddi (nc) mdb md (nc) 64 63 62 61 60 59 tst2 tst1 xt0 xt1 reset osc0 seg4 seg5 seg6 seg7 seg8 seg9 103 104 105 106 107 108 pin configuration (top view) (ml63189b) 128-pin plastic qfp note: pins marked as (nc) are no-connection pins which are left open.
? semiconductor ML63187/63189b 10/35 pad configuration (ml63189b) pad layout chip size : 4.81 mm 5.20 mm chip thickness : 350 m m (280 m m: available as required) coordinate origin : center of chip pad hole size : 100 m m 100 m m pad size : 110 m m 110 m m minimum pad pitch : 140 m m note: the chip substrate voltage is v ss . 64 com10 31 seg32 y x seg1 123 92 mdb seg2 1 63 com9 seg31 30 32 seg33 seg0 122 33 seg34 com8 121 34 seg35 com7 120 35 seg36 com6 119 36 seg37 com5 118 37 seg38 com4 117 38 seg39 com3 116 39 seg40 com2 115 40 seg41 com1 114 41 seg42 p0.3 113 42 seg43 p0.2 112 43 seg44 p0.1 111 44 seg45 p0.0 110 45 seg46 p9.3 109 46 seg47 p9.2 108 47 seg48 p9.1 107 48 seg49 p9.0 106 49 seg50 pa.3 105 50 seg51 pa.2 104 51 seg52 pa.1 103 52 seg53 pa.0 102 53 seg54 pb.3 101 54 seg55 pb.2 100 55 seg56 pb.1 99 56 seg57 pb.0 98 57 seg58 pe.3 97 58 seg59 pe.2 96 59 seg60 pe.1 95 60 seg61 pe.0 94 61 seg62 62 seg63 v ddi 93 seg30 29 65 com11 seg29 28 66 com12 seg28 27 67 com13 seg27 26 68 com14 seg26 25 69 com15 seg25 24 70 com16 seg24 23 71 v ss seg23 22 72 v dd1 seg22 21 73 v dd2 seg21 20 74 v dd3 seg20 19 75 v dd4 seg19 18 76 v dd5 seg18 17 77 c1 seg17 16 78 c2 seg16 15 79 v ddh seg15 14 80 cb1 seg14 13 81 cb2 seg13 12 82 v dd seg12 11 83 v ddl seg11 10 84 osc1 seg10 9 85 osc0 seg9 8 86 reset seg8 7 87 xt1 seg7 6 88 xt0 seg6 5 89 tst1 seg5 4 90 tst2 seg4 3 91 md seg3 2 ml63189b
? semiconductor ML63187/63189b 11/35 pad coordinates (ml63189b) pad no. pad name x (m) y (m) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 pad no. pad name x (m) y (m) 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 pad no. pad name x (m) y (m) 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 37 38 39 40 41 73 74 75 76 77 108 78 79 80 81 82 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 seg40 seg41 C2259 632 772 913 1053 1193 1334 1474 1615 1755 1895 C1895 C1755 C1615 C1474 C1334 C1193 C1053 C913 C772 C632 C491 C351 C211 C70 70 211 351 491 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 C2438 C2176 C2036 C1895 C1755 C1615 C1474 C1334 C1193 C1053 C913 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 C2438 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 com9 com10 com11 com12 com13 com14 com15 com16 v ss v dd1 v dd2 v dd3 v dd4 v dd5 c1 v ddh cb1 c2 C632 C491 C351 C211 C70 70 211 351 491 632 772 913 1053 1193 1334 1474 1615 1755 1895 2036 2176 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 1895 1755 1615 1474 1334 1193 1053 913 772 632 491 351 211 70 C211 C351 C70 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 v ddl osc1 osc0 reset xt1 xt0 tst1 tst2 md mdb v ddi pe.0 pe.1 pe.2 pe.3 pb.0 pb.1 pb.2 pb.3 pa.0 C772 C913 C1053 C1193 C1334 C1474 C1615 C1775 C1895 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 2132 1895 1755 1615 1474 1334 1193 1053 913 772 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 pa.1 pa.2 pa.3 p9.0 p9.1 p9.2 p9.3 p0.0 p0.1 p0.2 p0.3 com1 com2 com3 com4 com5 com6 com7 com8 seg0 seg1 632 491 351 211 70 C70 C211 C351 C491 C632 C772 C913 C1053 C1193 C1334 C1474 C1615 C1755 C1895 C2036 C2176 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 C2259 seg42 2259 C772 cb2 2438 C491 v dd 2438 C632
? semiconductor ML63187/63189b 12/35 pin descriptions the basic functions of each pin of the ML63187/ml63189b are described in table 1. a symbol with a slash (/) denotes a pin that has a secondary function. refer to table 2 for secondary functions. for type, "" denotes a power supply pin, "i" an input pin, "o" an output pin, and "i/o" an input- output pin. table 1 pin descriptions (basic functions) function symbol pin no. type v dd v ss v dd1 v dd2 v dd3 v dd4 power supply v dd5 c1 c2 v ddi v ddl v ddh cb1 cb2 xt0 i oscillation xt1 o osc0 i osc1 o description positive power supply negative power supply power supply pins for lcd bias (internally generated). capacitors (0.1 m f) should be connected between these pins and v ss . capacitor connection pins for lcd bias generation. a capacitor (0.1 m f) should be connected between c1 and c2. positive power supply pin for external interface (power supply for input, and input-output ports) positive power supply pin for internal logic (internally generated). a capacitor (0.1 m f) should be connected between this pin and v ss . voltage multiplier pin for power supply backup (internally generated). a capacitor (1.0 m f) should be connected between this pin and v ss . pins to connect a capacitor for voltage multiplier. a capacitor (1.0 m f) should be connected between cb1 and cb2. low-speed clock oscillation pins. an option for using crystal oscillation or rc oscillation is chosen by the mask option. if the crystal oscillation is chosen, a crystal should be connected between xt0 and xt1, and capacitor (c g ) should be connected between xt0 and v ss . if the rc oscillation is chosen, external oscillation resistor (r osl ) should be connected between xt0 and xt1. high-speed clock oscillation pins. a ceramic resonator and capacitors (c l0 , c l1 ) or external oscillation resistor (r osh ) should be connected to these pins. 56 45 46 47 48 49 50 51 52 69 57 53 54 55 62 61 59 58 pad no. 82 71 72 73 74 75 76 77 78 93 83 79 80 81 88 87 85 84 ml63189b ML63187 54 43 44 45 46 47 48 49 50 70 55 51 52 53 60 59 57 56 72 61 62 63 64 65 66 67 68 83 73 69 70 71 78 77 75 74 ml63189b ML63187
? semiconductor ML63187/63189b 13/35 table 1 pin descriptions (basic functions) (continued) function symbol pad no. type description p0.0/int5 110 p0.1/int5 111 p0.2/int5 112 p0.3/int5 113 p9.0 106 p9.1 107 p9.2 108 p9.3 109 pa.0 102 pa.1 103 pa.2 104 pa.3 105 pb.0/int0/ tm0cap/ tm0ovf 98 pb.1/int0/ tm1cap/ tm1ovf 99 pb.2/int0/t02ck 100 pb.3/int0/t13ck 101 pe.0/sin 94 pe.1/sout 95 pe.2/sclk 96 pe.3/int2 97 port 4-bit input ports. pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. applied to the ml63189b only. 4-bit input-output ports. in input mode, pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. in output mode, p-channel open drain output, n-channel open drain output, cmos output, or high-impedance output is selectable for each bit. p9.0 to p9.3 and pa.0 to pa.3 are applied to the ml63189b only. i i/o i/o i/o i/o pin no. 86 87 88 89 82 83 84 85 78 79 80 81 74 75 76 77 70 71 72 73 ml63189b ML63187 md 91 mdb 92 melody output pin (non-inverted output) 66 67 o o melody output pin (inverted output) melody reset 86 60 i reset reset input pin. setting this pin to "h" level puts this device into a reset state. then, setting this pin to "l" level starts executing an instruction from address 0000h. a pull-down resistor is internally connected to this pin. test tst1 i tst2 i input pins for testing. a pull-down resistor is internally connected to these pins. the user cannot use these pins. 63 64 89 90 88 89 90 91 84 85 86 87 81 82 76 79 80 ml63189b ML63187 75 76 77 78 71 72 73 74 63 64 58 61 62
? semiconductor ML63187/63189b 14/35 table 1 pin descriptions (basic functions) (continued) function symbol pad no. type description com1 114 com2 115 com3 116 com4 117 com5 118 com6 119 com7 120 com8 121 com9 63 com10 64 com11 65 com12 66 com13 67 com14 68 com15 69 com16 70 seg0 122 seg1 123 seg2 1 seg3 2 seg4 3 seg5 4 seg6 5 seg7 6 seg8 7 seg9 8 seg10 9 seg11 10 seg12 11 seg13 12 seg14 13 seg15 14 seg16 15 seg17 16 seg18 17 seg19 18 seg20 19 seg21 20 seg22 21 seg23 22 seg24 23 o lcd segment signal output pins o lcd common signal output pins lcd pin no. 90 91 92 93 94 95 96 97 36 37 39 40 41 42 43 44 98 99 100 101 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 ML63187 ml63189b ML63187 ml63189b 92 93 94 95 96 97 98 99 53 54 55 56 57 58 59 60 100 101 102 103 104 105 106 107 108 109 110 111 1 2 3 4 5 6 7 8 9 10 11 12 13 79 80 81 82 83 84 85 86 31 32 33 34 39 40 41 42 87 88 89 90 91 92 93 94 95 96 97 98 103 104 105 106 107 108 109 110 111 112 113 114 115
? semiconductor ML63187/63189b 15/35 table 1 pin descriptions (basic functions) (continued) function symbol pad no. type description seg25 24 seg26 25 seg27 26 seg28 27 seg29 28 seg30 29 seg31 30 seg32 31 seg33 32 seg34 33 seg35 34 seg36 35 seg37 36 seg38 37 seg39 38 seg40 39 seg41 40 seg42 41 seg43 42 seg44 43 seg45 44 seg46 45 seg47 46 seg48 47 seg49 48 seg50 49 seg51 50 seg52 51 seg53 52 seg54 53 seg55 54 seg56 55 seg57 56 seg58 57 seg59 58 seg60 59 seg61 60 seg62 61 seg63 62 o lcd segment signal output pins lcd pin no. 124 125 126 127 128 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 ml63189b ML63187 ml63189b ML63187 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 116 117 118 119 120 121 122 123 124 125 126 127 128 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
? semiconductor ML63187/63189b 16/35 table 2 shows the secondary functions of each pin of the ML63187/ml63189b. table 2 pin descriptions (secondary functions) function symbol pad no. type description external interrupt pb.0/int0 98 pb.1/int0 99 pb.2/int0 100 pb.3/int0 101 i p0.0/int5 110 p0.1/int5 111 p0.2/int5 112 p0.3/int5 113 external 0 interrupt input pins. the change of input signal level causes an interrupt to occur. the port b interrupt enable register (pbie) enables or disables an interrupt for each bit. external 5 interrupt input pins. the change of input signal level causes an interrupt to occur. the port 0 interrupt enable register (p0ie) enable or disable an interrupt for each bit. applied to the ml63189b only. i pe.3/int2 97 external 2 interrupt input pin. the change of input signal level causes an interrupt to occur. i pin no. 74 75 76 77 86 87 88 89 73 ml63189b ML63187 ml63189b ML63187 88 89 90 91 87 75 76 77 78 74
? semiconductor ML63187/63189b 17/35 table 2 pin descriptions (secondary functions) (continued) function symbol pin no. type description timer 0 overflow flag output pin. timer 1 overflow flag output pin. external clock input pin for timer 0 and timer 2. external clock input pin for timer 1 and timer 3. shift register receive data input pin. shift register transmit data output pin. shift register clock input-output pin. clock output when this device is used as a master processor. clock input when this device is used as a slave processor. pb.0/tm0ovf 74 o pb.1/tm1ovf 75 o pb.2/t02ck 76 i pb.3/t13ck 77 i pe.0/sin 70 i pe.1/sout 71 o pe.2/sclk 72 i/o timer shift register timer 0 capture input pin. timer 1 capture input pin. pb.0/tm0cap 74 i pb.1/tm1cap 75 i pad no. 98 99 100 101 94 95 96 98 99 ml63189b ML63187 capture ml63189b ML63187 75 76 77 78 71 72 73 75 76 88 89 90 91 84 85 86 88 89
? semiconductor ML63187/63189b 18/35 absolute maximum ratings parameter symbol condition rating unit C0.3 to +1.6 power supply voltage 1 ta = 25c v dd1 v C0.3 to +2.9 power supply voltage 2 ta = 25c v dd2 v C0.3 to +4.2 power supply voltage 3 ta = 25c v dd3 v C0.3 to +5.5 power supply voltage 4 ta = 25c v dd4 v C0.3 to +6.8 power supply voltage 5 ta = 25c v dd5 v power supply voltage 6 v dd C0.3 to +6.0 power supply voltage 7 ta = 25c v ddi v C0.3 to +6.0 power supply voltage 8 ta = 25c v ddh v C0.3 to v dd + 0.3 input voltage 1 v dd input, ta = 25c v in1 v C0.3 to v ddi + 0.3 input voltage 2 v ddi input, ta = 25c v in2 v C0.3 to v dd1 + 0.3 output voltage 1 v dd1 output, ta = 25c v out1 v C0.3 to v dd2 + 0.3 output voltage 2 v dd2 output, ta = 25c v out2 v C0.3 to v dd3 + 0.3 output voltage 3 v dd3 output, ta = 25c v out3 v C0.3 to v dd4 + 0.3 output voltage 4 v dd4 output, ta = 25c v out4 v C0.3 to v dd5 + 0.3 output voltage 5 v dd5 output, ta = 25c v out5 v C0.3 to v dd + 0.3 output voltage 6 v dd output, ta = 25c v out6 v C0.3 to v ddi + 0.3 output voltage 7 v ddi output, ta = 25c v out7 v C0.3 to v ddh + 0.3 output voltage 8 v ddh output, ta = 25c v out8 v C55 to +150 storage temperature t stg c (v ss = 0 v) C0.3 to +6.0 power supply voltage 9 ta = 25c v ddl v C0.3 to +6.0 ta = 25c v
? semiconductor ML63187/63189b 19/35 v ddi 0.9 to 5.5 v crystal oscillation frequency f xt 32.768 to 76.8 khz ceramic oscillation frequency f cm 300k to 500k v dd = 1.2 to 2.7 v c g = 5 to 25 pf parameter symbol condition range unit operating temperature t op C20 to +70 c v dd 0.9 to 2.7 v operating voltage (v ss = 0 v) high-speed rc oscillation frequency f rosh 200k 30% r osh = 100 k w not applied hz v dd = 0.9 to 1.2 v not applied hz r osh = 400 k w low-speed rc oscillation frequency f rosl khz 200k to 1m v dd = 1.5 to 2.7 v 700k 30% r osh = 75 k w 1m 30% v dd = 0.9 to 1.2 v 60 30% r osl = 700 k w 32 30% r osl = 1.5 m w 80 30% r osl = 500 k w v dd = 1.2 to 2.7 v recommended operating conditions ? when backup is used v ddi 1.8 to 5.5 v crystal oscillation frequency f xt 32.768 to 76.8 khz ceramic oscillation frequency f cm hz c g = 5 to 25 pf parameter symbol condition range unit operating temperature t op C20 to +70 c v dd 1.8 to 5.5 v operating voltage (v ss = 0 v) high-speed rc oscillation frequency f rosh 1m 30% hz r osh = 75 k w 1.35m 30% r osh = 51 k w 200k to 2m v dd = 1.8 to 5.5 v 700k 30% r osh = 100 k w low-speed rc oscillation frequency f rosl 32 30% khz r osl = 1.5 m w 60 30% r osl = 700 k w 80 30% r osl = 500 k w v dd = 1.8 to 5.5 v v dd = 1.8 to 3.5 v, r osh = 30 k w 2m 30% ? when backup is not used
? semiconductor ML63187/63189b 20/35 ? typical characteristics of low-speed rc oscillation when backup is used/backup is not used (v dd = v ddi = 1.5 v/v dd = v ddi = 3.0 v) ? typical characteristics of high-speed rc oscillation when backup is used (v dd = v ddi = 1.5 v) 1000 100 10 100 1000 10000 f rosl [khz] r osl [k w ] 10000 1000 100 10 100 1000 f rosh [khz] r osh [k w ]
? semiconductor ML63187/63189b 21/35 ? typical characteristics of high-speed rc oscillation when backup is not used (v dd = v ddi = 3.0 v) 10000 1000 100 10 100 1000 f rosh [khz] r osh [k w ]
? semiconductor ML63187/63189b 22/35 electrical characteristics dc characteristics parameter symbol condition mea- suring circuit unit 1.9 1.8 1.7 v dd2 voltage max. typ. min. v dd2 1/5 bias, 1/4 bias (ta = 25c) v C4 v dd2 voltage temperature deviation d v dd2 mv/c typ.+ 0.3 3/2 v dd2 typ.C 0.3 v dd3 voltage v dd3 1/5 bias v typ.+ 0.4 2 v dd2 typ.C 0.4 v dd4 voltage v dd4 1/5 bias v typ.+ 0.5 5/2 v dd2 typ.C 0.5 v dd5 voltage v dd5 1/5 bias v 1.2 crystal oscillation start voltage v sta oscillation start time: within 5 seconds v 0.9 crystal oscillation hold voltage v hold backup v 5.0 0.1 crystal oscillation stop detect time t stop ms 25 5 external crystal oscillator capacitance c g pf 30 25 20 internal crystal oscillator capacitance c d pf 16 12 8 internal rc oscillator capacitance c os pf 30 external ceramic oscillator capacitance c l0, 1 csa2.00mg (murata mfg.-make) used v dd = 3.0 v pf 0.4 0.0 por voltage v por1 v dd = 1.5 v v 1 0.7 0.0 v dd = 3.0 v v 1.7 backup not used v 2.0 1.5 1.0 v ddl voltage v ddl high-speed clock oscillation stopped v 5.5 1.2 high-speed clock oscillation (v dd = 1.2 to 5.5 v) v v ddh 2.7 2.0 v ddh voltage (backup used) high-speed clock oscillation (ceramic oscillation, 1 mhz) v dd = 1.5 v v high-speed clock oscillation stopped v dd = 1.5 v 3.0 2.8 v (v dd = v ddi = 0.9 to 5.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) typ.+ 0.1 1/2 v dd2 typ.C 0.1 v dd1 voltage v dd1 1/5 bias, 1/4 bias v typ.+ 0.2 v dd2 typ.C 0.2 1/4 bias (connect v dd3 and v dd2 ) typ.+ 0.3 3/2 v dd2 typ.C 0.3 1/4 bias typ.+ 0.4 2 v dd2 typ.C 0.4 1/4 bias 1.5 1.2 non-por voltage v por2 v dd = 1.5 v v 3.0 2.0 v dd = 3.0 v v 2.50 2.40 2.30 bld judgment voltage v bldc ld1 = 1, ld0 = 1, ta = 25c 1.90 1.80 1.70 ld1 = 1, ld0 = 0, ta = 25c v 1.30 1.20 1.10 ld1 = 0, ld0 = 1, ta = 25c 1.15 1.05 0.95 ld1 = 0, ld0 = 0, ta = 25c C3.5 bld judgment voltage temperature deviation d v bldc v bldc = 2.40 v (ld1 = 1, ld0 = 1) C2.3 v bldc = 1.80 v (ld1 = 1, ld0 = 0) mv/c C1.6 v bldc = 1.20 v (ld1 = 0, ld0 = 1) C1.2 v bldc = 1.05 v (ld1 = 0, ld0 = 0)
? semiconductor ML63187/63189b 23/35 notes: 1. "t stop " indicates that if the crystal oscillator stops over the value of t stop , the system reset occurs. 2. "por" denotes power on reset. 3. "v por1 " indicates that por occurs when v dd falls from v dd to v por1 and again rises up to v dd . 4. "v por2 " indicates that por does not occur when v dd falls from v dd to v por2 and again rises up to v dd .
? semiconductor ML63187/63189b 24/35 parameter symbol condition mea- suring circuit (v dd = v ddi = 1.5 v, v ss = 0 v, 1/5 bias, ta = C20 to +70c unless otherwise specified) unit max. typ. min. 6.5 5 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) m a 5 4 supply current 2 i dd2 cpu is in halt state. lcd is in power down mode. (high-speed clock oscillation stopped) m a 18 16 supply current 3 i dd3 cpu is in operation at low-speed oscillation. (high-speed clock oscillation stopped) m a 1 10 5 8 4 ta = C20 to +50c ta = C20 to +50c ta = C20 to +70c ta = C20 to +70c 1000 800 supply current 4 i dd4 cpu is in operation at high-speed oscillation (rc oscillation, r osh = 100 k w ) m a 850 700 supply current 5 i dd5 cpu is in operation at high-speed oscillation (ceramic oscillation, 1 mhz) m a ta = C20 to +50c 20 16 m a ta = C20 to +70c dc characteristics (continued) ? when backup is used ? when backup is not used parameter symbol condition mea- suring circuit (v dd = v ddi = 3.0 v, v ss = 0 v, 1/5 bias, ta = C20 to +70c unless otherwise specified) unit max. typ. min. 3 2.2 supply current 1 i dd1 cpu is in halt state. (high-speed clock oscillation stopped) m a 2.5 1.8 supply current 2 i dd2 cpu is in halt state. lcd is in power down mode. (high-speed clock oscillation stopped) m a supply current 3 i dd3 1 5 2.2 4 1.8 ta = C20 to +50c ta = C20 to +50c ta = C20 to +70c ta = C20 to +70c 700 550 supply current 4 i dd4 cpu is in operation at high-speed oscillation (rc oscillation, r osh = 100 k w ) m a 1000 850 supply current 5 i dd5 cpu is in operation at high-speed oscillation (ceramic oscillation, 2 mhz) m a 9 7.5 cpu is in operation at low-speed oscillation. (high-speed clock oscillation stopped) m a 12 7.5 ta = C20 to +50c ta = C20 to +70c
? semiconductor ML63187/63189b 25/35 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = C20 to +70c unless otherwise specified) unit max. output current 1 (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) C0.4 ma 2 i oh1 v oh1 = v ddi C 0.5 v C1.0 ma C1.5 ma output current 2 (md, mdb) output current 4 (osc1) i oh4r v oh4r = v ddh C 0.5 v (rc oscillation) C0.25 ma output leakage current (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) i ooh v oh = v ddi 0.3 m a i ool v ol = v ss m a typ. C1.4 C3.5 C5.0 C1.3 min. C2.5 C6.0 C8.5 C2.5 C0.3 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v 2.5 ma i ol1 v ol1 = 0.5 v 6.0 ma 8.5 ma 1.4 3.0 3.7 0.4 1.0 1.5 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v C0.5 ma i oh2 v oh2 = v dd C 0.7 v C2.0 ma C4.0 ma C2.0 C6.0 C9.0 C4.0 C11.0 C14.0 v dd = 1.5 v v dd = 3.0 v v dd = v ddh = 5.0 v 4.0 ma i ol2 v ol2 = 0.7 v 11.0 ma 14.0 ma 2.0 5.5 7.0 0.5 2.0 4.0 v dd = 1.5 v v dd = 3.0 v v dd = v ddh = 5.0 v output current 3 (seg0 to seg63) (com1 to com16) C4 m a i ohm3 m a m a 4 m a i omh3s m a m a v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C0.5 ma C1.7 C3.5 i ol4r v ol4r = 0.5 v (rc oscillation) 2.5 ma 1.5 0.25 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v 3.5 ma 1.8 0.5 i oh4c v oh4c = v ddh C 0.5 v (ceramic oscillation) C100 m a C250 C500 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C200 m a C350 C800 i ol4c v ol4c = 0.5 v (ceramic oscillation) 800 m a 500 200 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v 1000 m a 700 400 i oh3 v oh3 = v dd5 C 0.2 v (v dd5 level) i ohm3s i oml3 i omh3 m a i oml3s m a i olm3 m a i olm3s m a i ol3 v ohm3 = v dd4 + 0.2 v (v dd4 level) v ohm3s = v dd4 C 0.2 v (v dd4 level) v omh3 = v dd3 + 0.2 v (v dd3 level) v omh3s = v dd3 C 0.2 v (v dd3 level) v oml3 = v dd2 + 0.2 v (v dd2 level) v oml3s = v dd2 C 0.2 v (v dd2 level) v olm3 = v dd1 + 0.2 v (v dd1 level) v olm3s = v dd1 C 0.2 v (v dd1 level) v ol3 = v ss + 0.2 v (v ss level) C4 4 C4 4 C4 4 C4 4 * : applied to the ml63189b only.
? semiconductor ML63187/63189b 26/35 parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = C20 to +70c unless otherwise specified) unit max. input current 1 (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) 45 m a 3 i ih1 v ih1 = v ddi (when pulled down) 260 m a 650 m a input current 3 (reset) i ih3 v ih3 = v dd 350 m a typ. 20 120 350 180 min. 2 30 70 10 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v C2 m a i il1 v il1 = v ss (when pulled up) C30 m a C70 m a C20 C120 C350 C45 C260 C650 v ddi = 1.5 v v ddi = 3.0 v v ddi = 5.0 v input current 2 (osc0) C30 m a i il2 v il2 = v ss (when pulled up) C200 m a C170 C450 C350 C750 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v v dd = 1.5 v v dd = 3.0 v 2400 m a 1100 150 i ih1z v ih1 = v ddi (in a high impedance state) 1.0 m a 0.0 i il1z v il1 = v ss (in a high impedance state) 0.0 m a C1.0 i ih2r v ih2r = v ddh (rc oscillation) 1.0 m a 0.0 i il2r v il2r = v ss (rc oscillation) 0.0 m a C1.0 4.0 m a i ih2c v ih2c = v ddh (ceramic oscillation) 10 m a 1.8 6 0.5 3 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v C0.5 m a i il2c v il2c = v ss (ceramic oscillation) C3 m a C1.8 C6 C4.0 C10 v dd = v ddh = 3.0 v v dd = v ddh = 5.0 v v dd = v ddh = 5.0 v 5.0 ma 2.7 0.5 i il3 v il3 = v ss 0.0 m a C1.0 input current 4 (tst1, tst2) i ih4 v ih4 = v dd 1500 m a 750 50 v dd = 1.5 v v dd = 3.0 v 5.5 ma 3.0 0.5 v dd = v ddh = 5.0 v 11.0 ma 6.5 2.0 i il4 v il4 = v ss 0.0 m a C1.0 dc characteristics (continued) * : applied to the ml63189b only.
? semiconductor ML63187/63189b 27/35 dc characteristics (continued) parameter symbol condition mea- suring circuit (v dd = v ddi = v ddh = 3.0 v, v dd1 = 1.1 v, v dd2 = 2.2 v, v dd3 = 3.3 v, v dd4 = 4.4 v, v dd5 = 5.5 v, ta = C20 to +70c unless otherwise specified) unit max. typ. min. input voltage 1 (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) v ddi = 1.5 v 1.2 1.5 v 4 v ih1 v ddi = 3.0 v 2.4 3.0 v v ddi = 5.0 v 4.0 5.0 v input voltage 2 (osc0) d v t2 input pin capacitance (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) c in 5pf hysteresis width 2 (reset, tst1, tst2) 1 v ddi = 1.5 v 0.0 0.3 v v il1 v ddi = 3.0 v 0.0 0.6 v v ddi = 5.0 v 0.0 1.0 v v dd = v ddh = 3.0 v 2.4 3.0 v v ih2 v dd = v ddh = 5.0 v 4.0 5.0 v v dd = v ddh = 3.0 v 0.0 0.6 v v il2 v dd = v ddh = 5.0 v 0.0 1.0 v input voltage 3 (reset, tst1, tst2) v dd = 1.5 v 1.35 1.5 v v ih3 v dd = 3.0 v 2.4 3.0 v v dd = 5.0 v 4.0 5.0 v v dd = 1.5 v 0.0 0.15 v v il3 v dd = 3.0 v 0.0 0.6 v v dd = 5.0 v 0.0 1.0 v v ddi = 1.5 v 0.05 0.1 0.3 v d v t1 v ddi = 3.0 v 0.2 0.5 1.0 v v ddi = 5.0 v 0.25 1.0 1.5 v hysteresis width 1 (p0.0 to p0.3)* (p9.0 to p9.3)* (pa.0 to pa.3)* (pb.0 to pb.3) (pe.0 to pe.3) v dd = 1.5 v 0.05 0.1 0.3 v v dd = 3.0 v 0.2 0.5 1.0 v v dd = 5.0 v 0.25 1.0 1.5 v * : applied to the ml63189b only.
? semiconductor ML63187/63189b 28/35 measuring circuit 1 measuring circuit 2 v ss a v ih v il *2 v dd v ddi v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output *3 v ddl *2 input logic circuit to determine the specified measuring conditions. *3 measured at the s p ecified out p ut p ins. c b12 cb1 cb2 c 12 c1 c2 osc0 q osc1 w *1 v ss a v dd v ddi v dd1 v c a v dd2 v c b v dd3 v c c v dd4 v c d v dd5 v c e v ddh v c h xt0 xt1 c g c a , c b , c c , c d , c e , c l , c 12 c b12 , c h c g c l0 c l1 ceramic resonator : 0.1 m f : 1 m f : 15 pf : 30 pf : 30 pf : csa2.00mg (2 mhz) csb1000j (1 mhz) (murata mfg.-make) c l0 c l1 q w q w *1 rc oscillator r osh ceramic oscillator ceramic resonator v ddl v c l 32.768 khz crystal
? semiconductor ML63187/63189b 29/35 measuring circuit 3 v ss v dd v ddi v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output a *4 v ddl measuring circuit 4 v ss v ih v il *4 v dd v ddi v dd1 v dd2 v dd3 v dd4 v dd5 v ddh input output *4 measured at the specified input pins. waveform monitoring v ddl
? semiconductor ML63187/63189b 30/35 ac characteristics (serial interface, shift register) (v dd = 0.9 to 5.5 v, v ddh = 1.8 to 5.5 v, v ss = 0 v, v ddi = 5.0 v, ta = C20 to +70 c unless otherwise specified) ac characteristics timing ("h" level = 4.0 v, "l" level = 1.0 v) parameter symbol condition unit sclk input fall time max. typ. min. t f m s 1.0 sclk input rise time t r m s 1.0 0.8 sclk input "l" level pulse width t cwl m s 0.8 sclk input "h" level pulse width t cwh m s 1.8 sclk input cycle time t cyc v ddi = 5 v to v dd m s sclk output cycle time t cyc1(o) cpu in operation state at 32.768 khz m s 30.5 t cyc2(o) cpu in operation at 2 mhz v dd = v ddh = 1.8 v to 3.5 v m s 0.5 sout output delay time t ddr c l = 10 pf m s 0.4 0.5 sin input setup time t ds m s 0.8 sin input hold time t dh m s sout (pe.1) sin (pe.0) t cyc t ddr t r t f t cwh t cwl t ddr t ds t ds t dh 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) 5 v (v ddi ) 0 v (v ss ) sclk (pe.2)
? semiconductor ML63187/63189b 31/35 application circuits (ML63187) note: v ddi is the power supply pin for the input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with power supply backup xt0 com1-16 xt1 v ddh v dd cb1 cb2 v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 r osh pb.3 pb.2 pb.1 pb.0 c b12 c v c g c 12 lcd crystal 32.768 khz c h 1.5 v c e c d c c c b c a buzzer ?crystal oscillation is selected as low-speed oscillation. ?rc oscillation is selected as high-speed oscillation. ?ports are powered from external memory power source. ?c v is an ic power supply bypass capacitor. ?values of c a , c b , c c , c d , c e , c l , c b12 , c 12 , c h , and c g , are for reference only. v ddi v ddl c l push sw 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 0.1 m f 0.1 m f 1.0 m f 5 to 25 pf ML63187 pe.3 pe.2 pe.1 pe.0 v dd
? semiconductor ML63187/63189b 32/35 note: v ddi is the power supply pin for the input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with no power supply backup application circuits (ML63187) xt0 com1-16 xt1 v ddh v dd v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 pb.3 pb.2 pb.1 pb.0 c v c g c 12 lcd crystal 32.768 khz v dd 5.0 v c e c d c c c b c a buzzer ?crystal oscillation is selected as low-speed oscillation. ?ceramic oscillation is selected as high-speed oscillation. ?ports, external memory, and ic share their power supply. ?c v is an ic power supply bypass capacitor. ?values of c a , c b , c c , c d , c e , c l , c 12 , c g , c l0 , and c l1 are for reference only. v ddi v dd c l0 30 pf c l1 30 pf ceramic resonator (example: 1 mhz) cb1 cb2 v ddl c l ML63187 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f open push sw 5 to 25 pf pe.3 pe.2 pe.1 pe.0
? semiconductor ML63187/63189b 33/35 application circuits (ml63189b) note: v ddi is the power supply pin for the input and input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with power supply backup xt0 com1-16 xt1 v ddh v dd cb1 cb2 v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 r osh p9.3 p9.2 p9.1 p9.0 pb.3 pb.2 pb.1 pb.0 pa.3 pa.2 pa.1 pa.0 c b12 c v c g c 12 lcd crystal 32.768 khz c h 1.5 v c e c d c c c b c a buzzer ?crystal oscillation is selected as low-speed oscillation. ?rc oscillation is selected as high-speed oscillation. ?ports are powered from external memory power source. ?c v is an ic power supply bypass capacitor. ?values of c a , c b , c c , c d , c e , c l , c b12 , c 12 , c h , and c g , are for reference only. v ddi v ddl c l push sw 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 1.0 m f 0.1 m f 0.1 m f 1.0 m f 5 to 25 pf ml63189b pe.3 pe.2 pe.1 pe.0 p0.3 p0.2 p0.1 p0.0 v dd
? semiconductor ML63187/63189b 34/35 note: v ddi is the power supply pin for the input and input-output ports. be sure to connect the v ddi pin either to the positive power supply pin (v dd ) of this device or to the positive power supply pin of the external memory. application circuit example with no power supply backup application circuits (ml63189b) xt0 com1-16 xt1 v ddh v dd v dd5 v dd4 v dd3 v dd2 v dd1 c1 c2 reset tst1 tst2 md mdb v ss seg0-63 osc0 osc1 p9.3 p9.2 p9.1 p9.0 pb.3 pb.2 pb.1 pb.0 pa.3 pa.2 pa.1 pa.0 c v c g c 12 lcd crystal 32.768 khz v dd 5.0 v c e c d c c c b c a buzzer ?crystal oscillation is selected as low-speed oscillation. ?ceramic oscillation is selected as high-speed oscillation. ?ports, external memory, and ic share their power supply. ?c v is an ic power supply bypass capacitor. ?values of c a , c b , c c , c d , c e , c l , c 12 , c g , c l0 , and c l1 are for reference only. v ddi v dd c l0 30 pf c l1 30 pf ceramic resonator (example: 1 mhz) cb1 cb2 v ddl c l ml63189b 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f open push sw 5 to 25 pf pe.3 pe.2 pe.1 pe.0 p0.3 p0.2 p0.1 p0.0
? semiconductor ML63187/63189b 35/35 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp128-p-1420-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.19 typ. mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-62

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